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1 LTC1286/ltc1298 micropower sampling 12-bit a/d converters in s0-8 packages n 12-bit resolution n 8-pin soic plastic package n low cost n low supply current: 250 m a typ. n auto shutdown to 1na typ. n guaranteed 3/4lsb max dnl n single supply 5v to 9v operation n on-chip sample-and-hold n 60 m s conversion time n sampling rates: 12.5 ksps (LTC1286) 11.1 ksps (ltc1298) n i/o compatible with spi, microwire, etc. n differential inputs (LTC1286) n 2-channel mux (ltc1298) n 3v versions available: ltc1285/ltc1288 the LTC1286/ltc1298 are micropower, 12-bit, succes- sive approximation sampling a/d converters. they typi- cally draw only 250 m a of supply current when converting and automatically power down to a typical supply current of 1na whenever they are not performing conversions. they are packaged in 8-pin so packages and operate on 5v to 9v supplies. these 12-bit, switched-capacitor, suc- cessive approximation adcs include sample-and-holds. the LTC1286 has a single differential analog input. the ltc1298 offers a software selectable 2-channel mux. on-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. this, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. these circuits can be used in ratiometric applications or with an external reference. the high impedance analog inputs and the ability to operate with reduced spans (to 1.5v full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. 5v 4.7 m f analog input ?n gnd v cc clk d out v ref LTC1286 mpu (e.g., 8051) p1.4 p1.3 p1.2 +in 0v to 5v range LTC1286/98 ?ta01 cs/shdn 6 5 8 7 3 4 1 2 serial data link n battery-operated systems n remote data acquisition n battery monitoring n handheld terminal interface n temperature measurement n isolated data acquisition sample frequency (hz) 0.1k 1 supply current ( m a) 10 100 1000 1k 10k 100k LTC1286/98 ?ta02 t a = 25? v cc = v ref = 5v f clk = 200khz descriptio n u 25 m w, s0-8 package, 12-bit adc samples at 200hz and runs off a 5v supply supply current vs sample rate features applicatio n s u typical applicatio n s n u
2 LTC1286/ltc1298 1298 1298i order part number LTC1286cn8 LTC1286in8 t jmax = 150 c, q ja = 130 c/w t jmax = 150 c, q ja = 175 c/w order part number package/order i n for m atio n w uu absolute m axi m u m ratings w ww (notes 1 and 2) power dissipation .............................................. 500mw operating temperature range LTC1286c/ltc1298c............................. 0 c to 70 c LTC1286i/ltc1298i ........................... C40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec.)................ 300 c supply voltage (v cc ) to gnd ................................... 12v voltage analog and reference ................ C0.3v to v cc + 0.3v digital inputs ......................................... C0.3v to 12v digital output ............................. C0.3v to v cc + 0.3v part marking 1286 1286i order part number ltc1298cn8 ltc1298in8 order part number part marking ltc1298cs8 ltc1298is8 LTC1286cs8 LTC1286is8 symbol parameter conditions min typ max units v cc supply voltage (note 3) LTC1286 4.5 9.0 v ltc1298 4.5 5.5 v f clk clock frequency v cc = 5v (note 4) 200 khz t cyc total cycle time LTC1286, f clk = 200khz 80 m s ltc1298, f clk = 200khz 90 m s t hdi hold time, d in after clk - v cc = 5v 150 ns t sucs setup time cs before first clk - (see operating sequence) LTC1286, v cc = 5v 2 m s ltc1298, v cc = 5v 2 m s t sudi setup time, d in stable before clk - v cc = 5v 400 ns t whclk clk high time v cc = 5v 2 m s t wlclk clk low time v cc = 5v 2 m s t whcs cs high time between data transfer cycles v cc = 5v 2 m s t wlcs cs low time during data transfer LTC1286, f clk = 200khz 75 m s ltc1298, f clk = 200khz 85 m s reco m e n ded operati n g co n ditio n s u u u u w w consult factory for military grade parts. 1 2 3 4 8 7 6 5 top view v ref +in ?n gnd v cc clk d out n8 package 8-lead plastic dip cs/shdn 1 2 3 4 8 7 6 5 top view ch0 ch1 gnd v cc (v ref ) clk d out d in n8 package 8-lead plastic dip cs/shdn 1 2 3 4 8 7 6 5 top view v cc (v ref ) clk d out d in ch0 ch1 gnd s8 package 8-lead plastic soic cs/shdn 1 2 3 4 8 7 6 5 top view v cc clk d out v ref +in ?n gnd s8 package 8-lead plastic soic cs/shdn t jmax = 150 c, q ja = 130 c/w t jmax = 150 c, q ja = 175 c/w
3 LTC1286/ltc1298 symbol parameter conditions min typ max units s/(n +d) signal-to-noise plus distortion ratio 1khz/7khz input signal 71/68 db thd total harmonic distortion (up to 5th harmonic) 1khz/7khz input signal C 84/C80 db sfdr spurious-free dynamic range 1khz/7khz input signal 90/86 db peak harmonic or spurious noise 1khz/7khz input signal C 90/C86 db f smpl = 12.5khz (LTC1286), f smpl = 11.1khz (ltc1298) (note 5) co n verter a n d m ultiplexer characteristics u w u (note 5) dy n a m ic accuracy u w symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v, i o = 10 m a l 4.0 4.64 v v cc = 4.75v, i o = 360 m a l 2.4 4.62 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz hi-z output leakage cs = high l 3 m a i source output source current v out = 0v C 25 ma i sink output sink current v out = v cc 45 ma r ref reference input resistance cs = v cc 5000 m w (LTC1286) cs = gnd 55 k w i ref reference current (LTC1286) cs = v cc l 0.001 2.5 m a t cyc 3 640 m s, f clk 25khz l 90 140 m a t cyc = 80 m s, f clk = 200khz l 90 140 m a i cc supply current cs = v cc l 0.001 3.0 m a LTC1286, t cyc 3 640 m s, f clk 25khz l 220 460 m a LTC1286, t cyc = 80 m s, f clk = 200khz l 260 500 m a ltc1298, t cyc 3 720 m s, f clk 25khz l 320 600 m a ltc1298, t cyc = 90 m s, f clk = 200khz l 360 640 m a (note 5) 1.5v to v cc + 0.05v 1.5v to 5.55v C0.05v to v cc + 0.05v LTC1286 ltc1298 parameter conditions min typ max min typ max units resolution (no missing codes) l 12 12 bits integral linearity error (note 6) l 3/4 2 3/4 2 lsb differential linearity error l 1/4 3/4 1/4 3/4 lsb offset error l 3/4 33/4 3 lsb gain error l 2 8 2 8 lsb analog input range (note 7 and 8) l v ref input range (LTC1286) 4.5 v cc 5.5v v (notes 7, 8, and 9) 5.5v < v cc 9v v analog input leakage current (note 10) l 1 1 m a digital a n d dc electrical characteristics u
4 LTC1286/ltc1298 symbol parameter conditions min typ max units t smpl analog input sample time see operating sequence 1.5 clk cycles f smpl (max) maximum sampling frequency LTC1286 l 12.5 khz ltc1298 l 11.1 khz t conv conversion time see operating sequence 12 clk cycles t ddo delay time, clk to d out data valid see test circuits l 250 600 ns t dis delay time, cs - to d out hi-z see test circuits l 135 300 ns t en delay time, clk to d out enable see test circuits l 75 200 ns t hdo time output data remains valid after clk c load = 100pf 230 ns t f d out fall time see test circuits l 20 75 ns t r d out rise time see test circuits l 20 75 ns c in input capacitance analog inputs, on channel 20 pf analog inputs, off channel 5 pf digital input 5 pf ac characteristics (note 5) the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: these devices are specified at 5v. for 3v specified devices, see ltc1285 and ltc1288. note 4: increased leakage currents at elevated temperatures cause the s/h to droop, therefore it is recommended that f clk 3 120khz at 85 c, f clk 3 75khz at 70 and f clk 3 1khz at 25 c. note 5: v cc = 5v, v ref = 5v and clk = 200khz unless otherwise specified. note 6: linearity error is specified between the actual end points of the a/d transfer curve. note 7: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below gnd or one diode drop above v cc . this spec allows 50mv forward bias of either diode for 4.5v v cc 5.5v. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. for 5.5v < v cc 9v, reference and analog input range cannot exceed 5.55v. if reference and analog input range are greater than 5.55v, the output code will not be guaranteed to be correct. note 8: the supply voltage range for the LTC1286 is from 4.5v to 9v, but the supply voltage range for the ltc1298 is only from 4.5v to 5.5v. note 9: recommended operating conditions note 10: channel leakage current is measured after the channel selection. typical perfor m a n ce characteristics u w shutdown supply current vs clock rate with cs high and cs low supply current vs sample rate sample rate (khz) 0.1k 1 10 100 1000 1k 10k 100k lt1286/98 g03 supply current (?) t a = 25? v cc = v ref = 5v f clk = 200khz LTC1286 ltc1298 supply current vs temperature temperature (?) ?5 200 supply current (?) 250 350 400 450 ?5 25 45 125 lt1286/98 g04 300 ?5 5 65 85 105 t a = 25? v cc = v ref = 5v f clk = 200khz ltc1298 f smpl =11.1khz LTC1286 f smpl =12.5khz frequency (khz) 1 0.002 supply current (?) 5 1 0 15 20 25 35 20 100 140 lt1286/98 g01 10 30 80 180 200 40 60 120 160 cs = 0 (after conversion) t a = 25? v cc = v ref = 5v cs = v cc
5 LTC1286/ltc1298 typical perfor m a n ce characteristics u w 0 0 .05 0 .15 ?.2 .25 ?.3 ?.5 0 .35 ?.1 ?.4 0 .45 reference voltage (v) 1 change in linearity (lsb) 23 4 5 lt1286/98 g10 1.5 2.5 3.5 4.5 t a = 25? v cc = 5v f clk = 200khz f smpl = 12.5khz frequency (khz) 0 0 reference current ( m a) 10 30 40 50 100 70 4 8 10 lt1286/98 g06 20 80 90 60 2 6 12 14 t a = 25? v cc = 5v v ref = 5v f clk = 200khz temperature (?) ?5 92 reference current (?) 92.5 93.5 94 94.5 ?5 25 45 125 lt1286/98 g07 93 ?5 5 65 85 105 95 v cc = v ref = 5v f smpl = 12.5khz f clk = 200khz t a = 25? reference current vs temperature reference voltage (v) 1 0 change in offset (lsb = 1/4096 v ref ) 0.5 1 1.5 2 23 4 5 lt1286/98 g08 2.5 3 1.5 2.5 3.5 4.5 t a = 25? v cc = 5v f clk = 200khz f smpl = 12.5khz change in offset vs reference voltage change in offset vs temperature temperature (?) -55 -3 change in offset (lsb) -2.5 -2 1.5 -1 -15 25 65 lt1286/98 g09 -0.5 0 -35 5 45 85 v cc = v ref = 5v f clk = 200khz f smpl = f smpl (max) change in linearity vs reference voltage change in gain vs reference voltage reference current vs sample rate (LTC1286) 0 ? ? ? ? ? ?0 ? ? ? ? reference voltage (v) 1 change in gain (lsb) 23 4 5 lt1286/98 g11 1.5 2.5 3.5 4.5 t a = 25? v cc = 5v f clk = 200khz f smpl = 12.5khz input frequency (khz) 1 0 effective number of bits (enobs) 8 7 10 9 12 11 10 100 1000 ltc 1286/98 g20 6 50 44 62 56 74 68 38 5 4 3 2 1 t a = 25? v cc = 5v f clk = 200khz f smpl = 12.5khz effective bits and s/(n + d) vs input frequency differential nonlinearity vs code peak-to-peak adc noise vs reference voltage reference voltage (v) 1 adc noise in lbss 1 1.5 5 lt1286/98 g15 0.5 0 2 3 4 2 t a = 25? v cc = 5v f clk = 200khz code 0 differential nonlinearity error (lbs) ?.0 ?.80 ?.60 ?.40 ?.20 0.40 0.60 0.80 1.0 0.20 0.00 2048 4096
6 LTC1286/ltc1298 typical perfor m a n ce characteristics u w input frequency (hz) 1 10k 100 attenuation (%) 80 90 60 70 40 50 20 30 100k 1m 10m ltc 1286/98 g26 0 10 t a = 25? v cc = v ref = 5v f smpl = 12.5khz attenuation vs input frequency spurious free dynamic range vs frequency s/(n+d) vs input level input frequency (hz) 1k 40 spurious free dynamic range (db) 50 60 70 80 10k 100k 1m ltc 1286/98 g27 30 20 10 0 90 100 t a = 25? v cc = v ref = 5v f smpl = 12.5khz input level (db) ?0 0 signal-to-noise plus distortion (db) 20 10 40 30 60 50 80 70 ?0 ?0 lt1286/98 g25 ?0 0 t a = 25? v cc = v ref = 5v f in = 1khz f smpl = 12.5khz 4096 point fft plot intermodulation distortion power supply feedthrough vs ripple frequency frequency (khz) 0 ?0 ?0 0 35 lt c 1286/98 g21 ?0 ?00 12 467 ?20 ?40 ?0 magnitude (db) t a = 25? v cc = v ref = 5v f in = 5khz f clk = 200khz f smpl = 12.5khz frequency (khz) 0 ?0 ?0 0 35 lt c 1286/98 g24 ?0 ?00 12 467 ?20 ?40 ?0 magnitude (db) t a = 25? v cc = v ref = 5v f 1 = 5khz f 2 = 6khz f smpl = 12.5khz ripple frequency (khz) feedthrough (db) ?0 0 1 100 1000 10000 ltc 1286/98 g22 ?00 10 t a = 25? v cc = 5v (v ripple = 20mv) v ref = 5v f clk = 200khz maximum clock frequency vs source resistance source resistance (k w ) 0.1 0 clock frequency (khz) 50 100 150 200 300 110 lt1286/98 g12 250 +input ?nput r source v in t a = 25? v cc = v ref = 5v sample and hold aquisition time vs source resistance source resistance ( w ) 10 100 1000 lt1286/98 g16 1 0.1 10000 100 s&h acquisition time (ns) 1000 10000 t a = 25? v cc = v ref = 5v +input ?nput r source + v in supply voltage (v) 5 9 lt1286/98 g13 6 7 8 250 clock frequency (khz) 260 270 280 300 290 t a = 25? v cc = v ref = 5v maximum clock frequency vs supply voltage
7 LTC1286/ltc1298 typical perfor m a n ce characteristics u w temperature (?) ?5 clock frequency (khz) 100 150 25 45 65 85 lt1286/98 ?g14 50 0 ?5 ?5 5 200 v cc = v ref = 5v supply voltage (v) 3 1 digital logic threshold voltage (v) 2 3 4567 ltc 1286/98 g17 89 t a = 25? temperature (?) ?0 leakage current (na) 1000 100 10 1 0.1 0.01 100 1196/98 g19 ?0 20 60 140 ?0 0 40 80 120 v cc = 5v v ref = 5v on channel off channel input channel leakage current vs temperature digital input logic threshold vs supply voltage minimum clock frequency for 0.1 lsb error vs temperature pi n fu n ctio n s uuu LTC1286 v ref (pin 1): reference input. the reference input defines the span of the a/d converter. in + (pin 2): positive analog input. in C (pin 3): negative analog input. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. cs/shdn (pin 5): chip select input. a logic low on this input enables the LTC1286. a logic high on this input disables and powers down the LTC1286. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer and determines conversion speed. v cc (pin 8): power supply voltage. this pin provides power to the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane. ltc1298 cs/shdn (pin 1): chip select input. a logic low on this input enables the ltc1298. a logic high on this input disables and powers down the ltc1298. ch0 (pin 2): analog input. ch1 (pin 3): analog input. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. d in (pin 5): digital data input. the multiplexer address is shifted into this input. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer and determines conversion speed. v cc /v ref (pin 8): power supply and reference voltage. this pin provides power and defines the span of the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane.
8 LTC1286/ltc1298 block diagra m w + c sample v cc (v cc /v ref ) cs/shdn clk d out in + (ch0) in (ch1) micropower comparator capacitive dac v ref gnd pin names in parentheses refer to the ltc1298 (d in ) bias and shutdown circuit sar serial port test circuits d out 1.4v 3k 100pf test point LTC1286/98 ?tc01 d out v ol v oh t r t f LTC1286/98 ?tc02 voltage waveforms for d out rise and fall times, t r , t f load circuit for t ddo , t r and t f load circuit for t dis and t en voltage waveforms for d out delay times, t ddo clk d out v il t ddo v ol v oh LTC1286/98 ?tc03 d out 3k 100pf test point v cc t dis waveform 2, t en t dis waveform 1 LTC1286/98 ?tc04
9 LTC1286/ltc1298 1234 ltc1298 d in clk d out start t en b11 v ol LTC1286/98 ?tc07 cs test circuits voltage waveforms for t dis voltage waveforms for t en voltage waveforms for t en d out waveform 1 (see note 1) v ih t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. LTC1286/98 ?tc05 LTC1286/98 ?tc06 cs LTC1286 1 clk d out t en b11 v ol 2 applicatio n i n for m atio n wu u u while the ltc1298 operates from a 4.5v to 5.5v supply. both the LTC1286 and the ltc1298 contain a 12-bit, switched-capacitor adc, a sample-and-hold, and a serial port (see block diagram). although they share the same basic design, the LTC1286 and ltc1298 differ in some respects. the LTC1286 has a differential input and has an external reference input pin. it can measure signals floating on a dc common-mode volt- age and can operate with reduced spans to 1v. reduc- ing the spans allows it to achieve 244 m v resolution. the ltc1298 has a two-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. the reference input is tied to the supply pin. overview the LTC1286 and ltc1298 are micropower, 12-bit, suc- cessive approximation sampling a/d converters. the LTC1286 typically draws 250 m a of supply current when sampling at 12.5khz while the ltc1298 nominally con- sumes 350 m a of supply current when sampling at 11.1 khz. the extra 100 m a of supply current on the ltc1298 comes from the reference input which is inten- tionally tied to the supply. supply current drops linearly as the sample rate is reduced (see supply current vs sample rate). the adcs automatically power down when not performing conversions, drawing only leakage current. they are packaged in 8-pin so and dip packages. the LTC1286 operates on a single supply from 4.5v to 9v,
10 LTC1286/ltc1298 applicatio n i n for m atio n wu u u serial interface the 2-channel ltc1298 communicates with micropro- cessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. the single channel LTC1286 uses a 3-wire interface (see operating sequence in figures 1 and 2). data transfer the clk synchronizes the data transfer with each bit being transmitted on the falling clk edge and captured on the rising clk edge in both transmitting and receiving systems. the LTC1286 does not require a configuration input word and has no d in pin. a falling cs initiates data transfer as shown in the LTC1286 operating sequence. after cs falls the second clk pulse enables d out . after one null bit the a/d conversion result is output on the d out line. bringing cs high resets the LTC1286 for the next data exchange. the ltc1298 first receives input data and then transmits back the a/d conversion result (half duplex). because of the half duplex operation, d in and d out may be tied together allowing transmission over just 3 wires: cs, clk and data (d in /d out ). data transfer is initiated by a falling chip select (cs) signal. after cs falls the ltc1298 looks for a start bit. after the start bit is received, the 3-bit input word is shifted into the d in input which configures the ltc1298 and starts the conversion. after one null bit, the result of the conversion is output on the d out line. at the end of the data exchange cs should be brought high. this resets the ltc1298 in preparation for the next data exchange. clk cs t cyc b11 b5 b6 b7 b8 b9 b10 b11 hi-z d out t conv t data hi-z t sucs null bit b4 b3 b2 b1 power down power down b0* null bit b10 b9 b8 t smpl (msb) (msb) clk cs t cyc b11* b5 b6 b7 b8 b9 b10 b11 hi-z d out t conv t data hi-z t sucs null bit LTC1286/98 ?f01 b4 b3 b3 b4 b5 b6 b7 b2 b2 b1 b0 b1 b10 b9 b8 t smpl *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely. *after completing the data transfer, if further clocks are applied with cs low, the adc will output lsb-first data then followed with zeros indefinitely. t data : during this time, the bias circuit and the comparator power down and the reference input becomes a high impedance node, leaving the clk running to clock out lsb-first data or zeroes. figure 1. LTC1286 operating sequence
11 LTC1286/ltc1298 applicatio n i n for m atio n wu u u figure 2. ltc1298 operating sequence example: differential inputs (ch + , ch C ) clk cs t cyc b5 b6 b7 b8 b9 b10 b11 hi-z d out t conv t data hi-z t sucs null bit b4 b3 b2 b1 power down b0* t smpl (msb) (msb) clk start odd/ sign sgl/ diff cs t cyc b11 b5 b6 b7 b8 b9 b10 b11 hi-z d out d in t conv t data hi-z t sucs null bit msbf LTC1286/98 ?f02 b4 b3 b3 b4 b5 b6 b7 b2 b2 b1 b0 b1 b10 b9 b8 t smpl *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely. don't care start odd/ sign d in don't care t data : during this time, the bias circuit and the comparator power down and the reference input becomes a high impedance node, leaving the clk running to clock out lsb-first data or zeroes. sgl/ diff msbf * power down msb-first data (msbf = 0) msb-first data (msbf = 1) d in 1 d in 2 d out 1 d out 2 cs shift mux address in 1 null bit shift a/d conversion result out ltc1096/98 ?ai01
12 LTC1286/ltc1298 start bit the first logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer. the ltc1298 will ignore all leading zeros which precede this logical one. after the start bit is received, the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. multiplexer (mux) address the bits of the input word following the start bit assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following tables. in single-ended mode, all input channels are measured with respect to gnd. applicatio n i n for m atio n wu u u input data word the LTC1286 requires no d in word. it is permanently configured to have a single differential input. the conver- sion result appears on the d out line. the data format is msb first followed by the lsb sequence. this provides easy interface to msb or lsb first serial ports. for msb first data the cs signal can be taken high after b0 (see figure 1). the ltc1298 clocks data into the d in input on the rising edge of the clock. the input data words are defined as follows: msbf bit is a logical zero, lsb first data will follow the normal msb first data on the d out line. (see operating sequence) transfer curve the LTC1286/ltc1298 are permanently configured for unipolar only. the input span and code assignment for this conversion type are shown in the following figures. msb first/lsb first (msbf) the output data of the ltc1298 is programmed for msb first or lsb first sequence using the msbf bit. when the msbf bit is a logical one, data will appear on the d out line in msb first format. logical zeros will be filled in indefinitely following the last data bit. when the operation with d in and d out tied together the ltc1298 can be operated with d in and d out tied together. this eliminates one of the lines required to communicate to the microprocessor (mpu). data is trans- mitted in both directions on a single wire. the processor pin connected to this data line should be configurable as either an input or an output. the ltc1298 will take control of the data line and drive it low on the 4th falling clk edge after the start bit is received (see figure 3). therefore the processor port line must be switched to an input before this happens to avoid a conflict. in the typical applications section, there is an example of interfacing the ltc1298 with d in and d out tied together to the intel 8051 mpu. output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb 1lsb 0v input voltage (v ref = 5.000v) 4.99878v 4.99756v 0.00122v 0v LTC1286/98 ?ai05 transfer curve 0v 1lsb v ref ?lsb v ref 4096 v ref ?lsb v ref v in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 LTC1286/98 ?ai04 1lsb = mux address sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + + gnd single-ended mux mode differential mux mode ltc1096/8 ?ai03 sgl/ diff odd/ sign msbf start mux address msb first/ lsb first ltc1096/9 ?ai02 ltc1298 channel selection output code
13 LTC1286/ltc1298 applicatio n i n for m atio n wu u u sample rate (khz) 0.1k 1 10 100 1000 1k 10k 100k lt1286/98 g03 supply current (?) t a = 25? v cc = v ref = 5v f clk = 200khz LTC1286 ltc1298 input becomes high impedance at the end of each conver- sion leaving the clk running to clock out the lsb first data or zeroes (see figures 1 and 2). if the cs is not running rail- to-rail, the input logic buffer will draw current. this current may be large compared to the typical supply current. to obtain the lowest supply current, bring the cs pin to ground when it is low and to supply voltage when it is high. when the cs pin is high (= supply voltage), the converter is in shutdown mode and draws only leakage current. the status of the d in and clk input have no effect on supply current during this time. there is no need to stop d in and clk with cs = high; they can continue to run without drawing current. minimize cs low time in systems that have significant time between conver- sions, lowest power drain will occur with the minimum cs low time. bringing cs low, transferring data as quickly as possible, and then bringing it back high will result in the lowest current drain. this minimizes the amount of time the device draws power. after a conversion the adc automatically shuts down even if cs is held low (see figures 1 and 2). if the clock is left running to clock out lsb-data or zero, the logic will draw a small current. figure 5 shows that the typical supply current with cs = ground varies from 1 m a at 1khz to 35 m a at 200khz. when cs = v cc , the logic is gated off and no supply current is drawn regardless of the clock frequency. shutdown the LTC1286/ltc1298 are equipped with automatic shut- down features. they draw power when the cs pin is low and shut down completely when that pin is high. the bias circuit and comparator powers down and the reference achieving micropower performance with typical operating currents of 250 m a and automatic shutdown between conversions, the LTC1286/ltc1298 achieves extremely low power consumption over a wide range of sample rates (see figure 4). the auto-shutdown allows the supply curve to drop with reduced sample rate. several things must be taken into account to achieve such a low power consumption. figure 4. automatic power shutdown between conversions allows power consumption to drop with sample rate. 1 2 3 4 cs clk data (d in /d out ) start sgl/diff odd/sign msbf b11 b10 msbf bit latched by ltc1298 ltc1298 controls data line and sends a/d result back to mpu mpu controls data line and sends mux address to ltc1298 processor must release data line after 4th rising clk and before the 4th falling clk ltc1298 takes control of data line on 4th falling clk LTC1286/98 f03 figure 3. ltc1298 operation with d in and d out tied together
14 LTC1286/ltc1298 figure 5. shutdown current with cs high is 1na typically, regardless of the clock. shutdown current with cs = ground varies from 1 m a at 1khz to 35 m a at 200khz. applicatio n i n for m atio n wu u u clock frequency the maximum recommended clock frequency is 200khz for the LTC1286/ltc1298 running off a 5v supply. with the supply voltage changing, the maximum clock fre- quency for the devices also changes (see the typical curve of maximum clock rate vs supply voltage). if the maxi- mum clock frequency is used, care must be taken to ensure that the device converts correctly. mixed supplies it is possible to have a microprocessor running off a 5v supply and communicate with the LTC1286 operating on a 9v supply. the requirement to achieve this is that the outputs of cs and clk from the mpu have to be able to trip the equivalent inputs of the LTC1286 and the output of d out from the LTC1286 must be able to toggle the equivalent input of the mpu (see typical curve of digital input logic threshold vs supply voltage). with the LTC1286 operating on a 9v supply, the output of d out may go between 0v and 9v. the 9v output may damage the mpu running off a 5v supply. the way to get around this possibility is to have a resistor divider on d out (figure 6) and connect the center point to the mpu input. it should be noted that to get full shutdown, the cs input of the LTC1286 must be driven to the v cc voltage to keep the cs input buffer from drawing current. an alternative is to leave cs low after a conversion, clock data until d out outputs zeros, and then stop the clock low. d out loading capacitive loading on the digital output can increase power consumption. a 100pf capacitor on the d out pin can add more than 50 m a to the supply current at a 200khz clock frequency. an extra 50 m a or so of current goes into charging and discharging the load capacitor. the same goes for digital lines driven at a high frequency by any logic. the c v f currents must be evaluated and the trouble- some ones minimized. operating on other than 5v supplies (LTC1286) the LTC1286 operates from 4.5v to 9v supplies and the ltc1298 operates from a 5v supply. to operate the LTC1286 on other than 5v supplies a few things must be kept in mind. input logic levels the input logic levels of cs, clk and d in are made to meet ttl on a 5v supply. when the supply voltage varies, the input logic levels also change. for the LTC1286 to sample and convert correctly, the digital inputs have to be in the proper logical low and high levels relative to the operating supply voltage (see typical curve of digital input logic threshold vs supply voltage). if achieving micropower consumption is desirable, the digital inputs must go rail-to- rail between supply voltage and ground (see achieving micropower performance section). frequency (khz) 1 0.002 supply current (?) 5 1 0 15 20 25 35 20 100 140 lt1286/98 g01 10 30 80 180 200 40 60 120 160 cs = 0 (after conversion) t a = 25? v cc = v ref = 5v cs = v cc +in ?n gnd v cc clk d out v ref 50k 50k 5v 4.7 m f mpu (e.g. 8051) 5v p1.4 p1.3 p1.2 LTC1286/98 ?f06 differential inputs common-mode range 0v to 5v 9v LTC1286 cs figure 6. interfacing a 9v powered LTC1286 to a 5v system
15 LTC1286/ltc1298 applicatio n i n for m atio n wu u u board layout considerations grounding and bypassing the LTC1286/ltc1298 are easy to use if some care is taken. they should be used with an analog ground plane and single point grounding techniques. the gnd pin should be tied directly to the ground plane. the v cc pin should be bypassed to the ground plane with a 10 m f tantalum capacitor with leads as short as possible. if the power supply is clean, the LTC1286/ltc1298 can also operate with smaller 1 m f or less surface mount or ceramic bypass capacitors. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. sample-and-hold both the LTC1286 and the ltc1298 provide a built-in sample-and-hold (s&h) function to acquire signals. the s&h of the LTC1286 acquires input signals from + input relative to C input during the t smpl time (see figure 1). however, the s&h of the ltc1298 can sample input signals in the single-ended mode or in the differential inputs during the t smpl time (see figure 7). single-ended inputs the sample-and-hold of the ltc1298 allows conversion of rapidly varying signals. the input voltage is sampled during the t smpl time as shown in figure 7. the sampling interval begins as the bit preceding the msbf bit is shifted in and continues until the falling clk edge after the msbf bit is received. on this falling edge, the s&h goes into hold mode and the conversion begins. figure 7. ltc1298 + and C input settling windows clk d in d out "+" input "? input sample hold "+" input must settle during this time t smpl t conv cs sgl/diff start msbf don't care 1st bit test "? input must settle during this time b11 ltc1096/8 ?f07
16 LTC1286/ltc1298 applicatio n i n for m atio n wu u u differential inputs with differential inputs, the adc no longer converts just a single voltage but rather the difference between two volt- ages. in this case, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the volt- age on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be per- formed accurately. the conversion time is 12 clk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input this error would be: v error (max) = v peak 2 p f(C) 12/f clk where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. in most cases v error will not be significant. for a 60hz signal on the C input to generate a 1/4lsb error (305 m v) with the converter running at clk = 200khz, its peak value would have to be 13.48mv. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the LTC1286/ ltc1298 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. however, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. + input settling the input capacitor of the LTC1286 is switched onto + input during the t smpl time (see figure 1) and samples the input signal within that time. however, the input capacitor of the ltc1298 is switched onto + input during the sample phase (t smpl , see figure 7). the sample phase is 1 1/2 clk cycles before conversion starts. the voltage on the + input must settle completely within t smple for the LTC1286 and the ltc1298 respectively. minimizing r source + and c1 will improve the input settling time. if a large + input source resistance must be used, the sample time can be increased by using a slower clk frequency. C input settling at the end of the t smpl , the input capacitor switches to the C input and conversion starts (see figures 1 and 7). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage settles completely during the first clk cycle of the conversion time and be free of noise. minimizing r source C and c2 will improve settling time. if a large C input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 7). again, the+ and C input sampling times can be extended as described above to accommodate slower op amps. most op amps, including the lt1006 and lt1413 single supply op amps, can be made to settle well even with the minimum settling windows of 6 m s (+ input) which occur at the maximum clock rate of 200khz. source resistance the analog inputs of the LTC1286/ltc1298 look like a 20pf capacitor (c in ) in series with a 500 w resistor (r on ) as shown in figure 8. c in gets switched between the selected + and C inputs once during each conversion cycle. large external source resistors and capacitances figure 8. analog input equivalent circuit r on = 500 w c in = 20pf LTC1286/98 ? input r source + v in + c1 input r source v in c2 LTC1286/98 ?f08
17 LTC1286/ltc1298 converter, the reference input should be driven by a reference with low r out (ex. lt1004, lt1019 and lt1021) or a voltage source with low r out . reduced reference operation the minimum reference voltage of the ltc1298 is limited to 4.5v because the v cc supply and reference are inter- nally tied together. however, the LTC1286 can operate with reference voltages below 1v. the effective resolution of the LTC1286 can be increased by reducing the input span of the converter. the LTC1286 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of change in linear- ity vs reference voltage and change in gain vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values: 1. offset 2. noise 3. conversion speed (clk frequency) offset with reduced v ref the offset of the LTC1286 has a larger effect on the output code. when the adc is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of change in offset vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 122 m v which is 0.1lsb with a 5v reference becomes 0.5lsb with a 1v reference and 2.5lsbs with a will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. rc input filtering it is possible to filter the inputs with an rc network as shown in figure 9. for large values of c f (e.g., 1 m f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = 20pf v in /t cyc and is roughly proportional to v in . when running at the minimum cycle time of 64 m s, the input current equals 1.56 m a at v in = 5v. in this case, a filter resistor of 75 w will cause 0.1lsb of full-scale error. if a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. r filter v in c filter LTC1286/98 ?f09 LTC1286 ? i dc figure 9. rc input filtering LTC1286 ref + r out v ref 1 4 gnd LTC1286/98 ?f10 figure 10. reference input equivalent circuit input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 m a (at 125 c) flowing through a source resistance of 240 w will cause a voltage drop of 240 m v or 0.2lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of input channel leakage current vs tem- perature). reference inputs the reference input of the LTC1286 is effectively a 50k w resistor from the time cs goes low to the end of the conversion. the reference input becomes a high impedence node at any other time (see figure 10). since the voltage on the reference input defines the voltage span of the a/d applicatio n i n for m atio n wu u u
18 LTC1286/ltc1298 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input of the LTC1286. noise with reduced v ref the total input referred noise of the LTC1286 can be reduced to approximately 400 m v peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. for operation with a 5v reference, the 400 m v noise is only 0.33lsb peak-to-peak. in this case, the LTC1286 noise will contribute virtually no uncertainty to the output code. however, for reduced references the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 2.5v reference this same 400 m v noise is 0.66lsb peak-to-peak. this will reduce the range of input volt- ages over which a stable output code can be achieved by 1lsb. if the reference is further reduced to 1v, the 400 m v noise becomes equal to 1.65lsbs and a stable code may be difficult to achieve. in this case averaging multiple readings may be necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup. conversion speed with reduced v ref with reduced reference voltages, the lsb step size is reduced and the LTC1286 internal comparator over- drive is reduced. therefore, it may be necessary to reduce the maximum clk frequency when low values of v ref are used. dynamic performance the LTC1286/ltc1298 have exceptional sampling capa- bility. fast fourier transform (fft) test techniques are used to characterize the adcs frequency response, dis- applicatio n i n for m atio n wu u u tortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 11 shows a typical LTC1286 plot. signal-to-noise ratio t he signal-to-noise plus distortion ratio (s/n + d) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other fre- quency components at the adcs output. the output is band limited to frequencies above dc and below one half the sampling frequency. figure 12 shows a typical spec- tral content with a 12.5khz sampling rate. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to s/(n+d) by the equation: enob = [s/(n + d) C 1.76]/6.02 where s/(n + d) is expressed in db. at the maximum sampling rate of 12.5khz with a 5v supply, the LTC1286 maintains above 11 enobs at 10khz input frequency. above 10khz the enobs gradually decline, as shown in figure 12, due to increasing second harmonic distortion. the noise floor remains low. frequency (khz) 0 ?0 ?0 0 35 lt c 1286/98 g21 ?0 ?00 12 467 ?20 ?40 ?0 magnitude (db) t a = 25? v cc = v ref = 5v f in = 5khz f clk = 200khz f smpl = 12.5khz figure 11. LTC1286 non-averaged, 4096 point fft plot
19 LTC1286/ltc1298 applicatio n i n for m atio n wu u u if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a + f b ) and (f a C f b ) while 3rd order imd terms include (2f a + f b ), (2f a C f b ), (f a + 2f b ), and (f a C 2f b ). if the two input sine waves are equal in magnitudes, the value (in db) of the 2nd order imd products can be expressed by the following formula: imd f f mplitude f f ab ab () = () ? ? 20log a amplitude at f a for input frequencies of 5khz and 6khz, the imd of the LTC1286/ltc1298 is 73db with a 5v supply. peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in dbs relative to the rms value of a full- scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input. the full-linear bandwidth is the input frequency at which the effective bits rating of the adc falls to 11 bits. beyond this frequency, distortion of the sampled input signal increases. the LTC1286/ltc1298 have been designed to optimize input bandwidth, allowing the adcs to undersample input signals with frequencies above the converters nyquist frequency. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half of the sampling frequency. thd is defined as: thd = ++++ 20log vvv v v 2 2 3 2 4 2 n 2 1 ... where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through the n th harmonics. the typical thd speci- fication in the dynamic accuracy table includes the 2nd through 5th harmonics. with a 7khz input signal, the LTC1286/ltc1298 have typical thd of 80db with v cc = 5v. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. figure 12. effective bits and s/(n + d) vs input frequency input frequency (khz) 1 0 effective number of bits (enobs) 8 7 10 9 12 11 10 100 1000 ltc 1286/98 g20 6 50 44 62 56 74 68 38 5 4 3 2 1 t a = 25? v cc = 5v f clk = 200khz f smpl = 12.5khz
20 LTC1286/ltc1298 microprocessor interfaces the LTC1286/ltc1298 can interface directly without ex- ternal hardware to most popular microprocessor (mpu) synchronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then 3 or 4 of the mpu's parallel port lines can be programmed to form the serial link to the LTC1286/ltc1298. included here is one serial interface example and one example showing a parallel port programmed to form the serial interface. motorola spi (mc68hc11) the mc68hc11 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfers data msb -first and in 8-bit increments. the d in word sent to the data register starts with the spi process. with three 8-bit transfers, the a/d result is read into the mpu. the second 8-bit transfer clocks b11 through b8 of the a/d conversion result into the processor. the third 8-bit transfer clocks the remaining bits, b7 through b0, into the mpu. the data is right justified into two memory locations. anding the second byte with of hex clears the four most significant bits. this operation was not included in the code. it can be inserted in the data gathering loop or outside the loop when the data is processed. mc68hc11 code in this example the d in word configures the input mux for a single-ended input to be applied to cho. the conversion result is output msb-first. typical applicatio n s n u table 1. microprocessor with hardware serial interfaces compatible with the LTC1286/ltc1298 part number type of interface motorola mc6805s2,s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd63705 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous hd64180 csi/o national semiconductor cop400 family microwire ? cop800 family microwire/plus ? ns8050u microwire/plus ? hpc16000 family microwire/plus ? texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020 serial port intel 8051 bit manipulation on parallel port * requires external hardware ? microwire and microwire/plus are trademarks of national semiconductor corp.
21 LTC1286/ltc1298 label mnemonic operand comments ldaa #$50 configuration data for spcr staa $1028 load data into spcr ($1028) ldaa #$1b config. data for port d ddr staa $1009 load data into port d ddr ldaa #$01 load din word into acc a staa $50 load din data into $50 ldaa #$a0 load din word into acc a staa $51 load din data into $51 ldaa #$00 load dummy din word into acc a staa $52 load dummy din data into $52 ldx #$1000 load index register x with $1000 loop bclr $08,x,#$01 d0 goes low (cs goes low) ldaa $50 load din into acc a from $50 staa $102a load din into spi, start sck ldaa $1029 check spi status reg wait1 bpl wait1 check if transfer is done ldaa $51 load din into acc a from $51 staa $102a load din into spi, start sck wait2 ldaa $1029 check spi status reg bpl wait2 check if transfer is done ldaa $102a load ltc1291 msbs into acc a staa $62 store msbs in $62 ldaa $52 load dummy into acc a from $52 staa $102a load dummy din into spi, start sck wait3 ldaa $1029 check spi status reg bpl wait3 check if transfer is done bset $08,x#$01 do goes high (cs goes high) ldaa $102a load ltc1291 lsbs in acc staa $63 store lsbs in $63 jmp loop start next conversion label mnemonic operand comments timing diagram for interface to the mc68hc11 LTC1286/98 ai07 d out from ltc1298 stored in mc68hc11 ram b2 b1 b0 b3 b4 b6 b7 b5 0 0 lsb msb #62 #63 0 0 b11 b10 b9 b8 clk d out cs analog inputs d0 sck mc68hc11 d in miso ltc1298 ch0 ch1 byte 1 byte 2 mosi hardware and software interface to the mc68hc11 cs clk d out mpu received word LTC1286/98 ai06 sgl/ diff start b3 b7 b6 b5 b4 b2 b0 b1 b11 b10 b9 b8 d in mpu transmit word byte 3 (dummy) byte 2 00 00 sgl/ diff 1 byte 1 x odd/ sign msbf x x x x 000 x x x xx x x x byte 3 byte 2 byte 1 b11 ? ? ? 0 b10 b8 b9 b7 b6 b4 b5 b3 b2 b0 b1 don't care odd/ sign ? ?? ? ? ??? msbf typical applicatio n s n u
22 LTC1286/ltc1298 typical applicatio n s n u interfacing to the parallel port of the intel 8051 family the intel 8051 has been chosen to demonstrate the interface between the ltc1298 and parallel port micro- processors. normally the cs, clk and d in signals would be generated on 3 port lines and the d out signal read on a 4th port line. this works very well. however, we will demonstrate here an interface with the d in and d out of the ltc1298 tied together as described in the serial inter- face section. this saves one wire. the 8051 first sends the start bit and mux address to the ltc1298 over the data line connected to p1.2. then p1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 12-bit a/d result over the same data line. label mnemonic operand comments mov a, #ffh d in word for ltc1298 setb p1.4 make sure cs is high clr p1.4 cs goes low mov r4, #04 load counter loop 1 rlc a rotate d in bit into carry clr p1.3 sclk goes low mov p1.2, c output d in bit to ltc1298 setb p1.3 sclk goes high djnz r4, loop 1 next bit mov p1, #04 bit 2 becomes an input clr p1.3 sclk goes low mov r4, #09 load counter loop 2 mov c, p1.2 read data bit into carry rlc a rotate data bit into acc. setb p1.3 sclk goes high clr p1.3 sclk goes low djnz r4, loop 2 next bit mov r2, a store msbs in r2 clr a clear acc. mov r4, #04 load counter loop 3 mov c, p1.2 read data bit into carry rlc a rotate data bit into acc. setb p1.3 sclk goes high clr p1.3 sclk goes low djnz r4, loop 3 next bit mov r4, #04 load counter loop 4 rrc a rotate right into acc. djnz r4, loop 4 next rotate mov r3, a store lsbs in r3 setb p1.4 cs goes high d out from 1298 stored in 8501 ram msb r2 b11 b10 b9 b8 b7 b6 b5 b4 lsb r3 b3 b2 b1 b0 0 0 0 0 cs clk d out d in ltc1298 analog inputs p1.4 p1.3 p1.2 8051 mux address a/d result LTC1286/98 ta01 clk msbf bit latched into ltc1298 8051 p1.2 outputs data to ltc1298 ltc1298 sends a/d result back to 8051 p1.2 ltc1298 takes control of data line on 4th falling clk 8051 p1.2 reconfigured as in input after the 4th rising clk and before the 4th falling clk msbf b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sgl/ diff start data ( d in /d out ) LTC1286/98 ta02 cs odd/ sign
23 LTC1286/ltc1298 a quick look circuit for the LTC1286 users can get a quick look at the function and timing of the lt1286 by using the following simple circuit (figure 13). v ref is tied to v cc . v in is applied to the +in input and the Cin input is tied to the ground. cs is driven at 1/16 the clock rate by the 74c161 and d out outputs the data. the output data from the d out pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of cs (figure 14). note the lsb data is partially clocked out before cs goes high. typical applicatio n s n u micropower battery voltage monitor a common problem in battery systems is battery voltage monitoring. this circuit monitors the 10 cell stack of nicad or nimh batteries found in laptop computers. it draws only 67 m a from the 5v supply at f smpl = 0.1khz and 25 m a to 55 m a from the battery. the 12-bits of resolution of the LTC1286 are positioned over the desired range of 8v to 16v. this is easily accomplished by using the adcs differential inputs. tying the Cinput to the reference gives an adc input span of v ref to 2v ref (2.5v to 5v). the resistor divider then scales the input voltage for 8v to 16v. figure 13. quick look circuit for the LTC1286 clr clk a b c d p gnd v cc rc qa qb qc qd t load 74c161 v in to oscilloscope clock in 250khz LTC1286/98 f13 v cc clk d out LTC1286 +in ?n gnd 4.7 m f 5v 5v v ref cs figure 14. scope trace the LTC1286 quick look circuit showing a/d output 101010101010 (aaa hex ) figure 15. micropower battery voltage monitor 39k 5v lt1004-2.5 200k 91k 3 w battery monitor input 8v to 16v 1 m f 0.1 m f cs clk d out LTC1286 LTC1286/98 f15 ?n v cc v ref gnd +in msb (b11) vertical: 5v/div horizontal: 10?/div lsb (b0) null bit LTC1286/98 f14 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 LTC1286/ltc1298 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1994 sn128698 128698fs lt/gp 0394 10k ? printed in usa dimensions in inches (millimeters) unless otherwise noted. package descriptio n u n8 package 8-lead plastic dip 0.045 ?0.015 (1.143 ?0.381) 0.100 ?0.010 (2.540 ?0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 ?0.005 (3.302 ?0.127) 0.020 (0.508) min 0.018 ?0.003 (0.457 ?0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.250 ?0.010 (6.350 ?0.254) 0.400 (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.320 (7.620 ?8.128) 0.325 +0.025 0.015 +0.635 0.381 8.255 () 1 2 3 4 0.150 ?0.157* (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) so8 0294 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 8?typ 0.008 ?0.010 (0.203 ?0.254) 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). s8 package 8-lead plastic soic

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